Digital modulators are widely used in digital communication systems, such as, for example, digital wireless systems and digital cable systems. Various standards govern the various types of communications systems. Each set of standards specifies a particular symbol rate to be used to transmit and receive information. FIG. 1 illustrates a block diagram of a known digital modulator 1. The digital modulator 1 has a multi-stage upsampling filter 2 and an output sampling rate stage 3. The multi-stage upsampling filter 2 comprises a square root raised cosine (SRRC) filter 4 that performs pulse shaping, and M stages of interpolation filters 5 and 6 for upsampling the signal output from the SRRC filter 4 to convert the signal to a rate that is relatively close to the final output rate produced by the output sampling rate stage 3. For ease of illustration, only two interpolation stages 5 and 6 are shown in FIG. 1, although more than two interpolation stages are typically used.
The output sampling rate stage 3 includes a sample rate converter 7 for further interpolation from a sampling rate that is an integer multiple of the symbol rate, FIN=NM*FSYM, to the arbitrary output sampling rate not related to the symbol rate, FOUT. This final stage 7 of interpolation requires its interpolation ratio to be continuously variable. If a digital intermediate frequency (IF) architecture is used, the base-band signal will be translated to the desired IF frequency using a quadrature direct digital frequency synthesizer (QDDFS) 8. The digital-to-analog converter (DAC) 9 receives the signal output from the QDDFS 8 at a sample rate of FOUT and produces an analog output signal.
The M interpolation filter stages 5 and 6 that perform interpolation from the input symbol rate, FSYM, to the input sampling rate, FIN=NM*FSYM, of the output sampling rate stage 3 are related to the symbol rate FSYM by a factor of N1 and N2, respectively, where M=2. The factor NM is equal to the cumulative product of the interpolation ratio of each interpolation filter stage. The sample rate converter 7 further interpolates the signal from FIN=NM*FSYM to a new sampling rate FOUT.
FIG. 2 illustrates a block diagram of the sample rate converter 7 shown in FIG. 1. The sample rate converter 7 comprises a numerically controlled oscillator (NCO) 11, which supplies the interpolation interval μk to a Farrow Structure 15, and generates the reference clocks, CLKREF1 and CLKREF2, to the interpolation filter stages 5 and 6. The reference clocks of the interpolation filter stages have various frequencies equal to Ni times the symbol clock, where Ni is the ratio between the output sampling rate of the ith interpolation stage and the original symbol rate. The Farrow Structure 15 is a well-known computational block that performs polynomial-based interpolation.
The NCO 11 is implemented using a digital accumulator 12. One input of the accumulator 12 is the frequency control word (FCW), which is equal to FIN/FOUT. On every clock cycle, the accumulator 12 adds the FCW to the accumulated results from the previous clock cycle, which are stored in register 13. When FCW is less than or equal to 0.5, the most significant bit (MSB) of the accumulated results toggles at an effective rate that is equal to the input clock rate, FIN, which is the output rate of the multi-stage upsampling filter 2. This clock is further divided by a divider 14 to generate the clocks CLKREF1 and CLKREF2 of the interpolation filter stages 5 and 6 of the multi-stage upsampling filter 2 shown in FIG. 1. Thus, the clocks of the interpolation filter stages 5 and 6 differ only by integer times.
A number L of the MSBs of the accumulated results output from register 13 are used to calculate the polynomial coefficients used by the Farrow Structure 15. The Farrow Structure 15 performs polynomial-based interpolation by multiplying its input, which has a sample rate of FIN, by the polynomial coefficients to produce the final output having a sample rate of FOUT. The value of μk, which corresponds to the interpolation interval for interpolating samples in between the original samples, is also derived from the accumulated results output from register 13.
In order to use the configuration of the NCO 11 shown in FIG. 2, FOUT needs to be at least twice as great as FIN. In addition, because each interpolation filter stage requires its own reference clock, the configuration shown in FIG. 2 cannot be easily implemented in software, if it can be implemented in software at all. Also, because the reference clocks of the interpolation filter stages are derived from the output sampling rate stage, the upsampling performed by the interpolation filter stages is necessarily coupled to the final output sample rate, FOUT.
A need exists for a method and apparatus for performing sample rate conversion that can be efficiently implemented in hardware and/or software, that do not require that the output sampling rate, FOUT, be at least twice as great as the input sampling rate, FIN, and that decouples the upsampling performed by the interpolation filter stages from the final output sample rate, FOUT.